library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity ROM is
generic (	N_DATA	: natural := 4;
		N_ROWS	: natural := 8);
port(	ADDR	: in	STD_LOGIC_VECTOR (N_DATA-1 downto 0);
		I		: out STD_LOGIC_VECTOR (N_DATA*2-1 downto 0)
);
type ROM_Array is array (0 to N_ROWS-1) of std_logic_vector (N_DATA*2 - 1 downto 0);
end ROM;

architecture Behav32 of ROM is
begin

	process(ADDR)
	variable Content	: ROM_Array;
	variable index		: natural;
	begin
		index := 0;

--PC=0				R(1) = 3 + R(0)	= 3
		Content(0)	:= "00010111";
--PC=1				jump to PC3	***************** long int 4 bit (done)
		Content(1)	:= "01110011";--	= 3
--PC=2				NOP
		Content(2)	:= "00000000";
--PC=3				R(0) = R(1) - 2
		Content(3)	:= "00101010";--	= 1
--PC=4				R(2) = R(1) * R(0)
		Content(4)	:= "10111010";--	= 3
--PC=5				MEM(3) = R(1)	***************** 2 reg 2 bits
		Content(5)	:= "1111-111";--	= 3
--PC=6				R(0) = R(0) +1
		Content(6)	:= "00010001";--	= 2
--PC=7				R(1) = MEM(3)
		Content(7)	:= "1000-111";--	= 3
	--mem operation can address all the 4 cache array, but only the first 2 of the rf
		
		index	 := to_integer(unsigned(ADDR));
		I		<= Content(index) ;

	end process;
end Behav32;
